PDC20230-C

Used in: Promise DC2000C, DC2300 controllers, Octek VL-Combo and by various OEMs (RT-1504-1): .
Manufacturer support: none.
Documentation available: none.
Drivers available: DOS, Win 3.1x, Win 95, WinNT 3.1, Netware 386 3.1x, 4.01, OS/2 2.0, 2.1x, SCO Unix, AT&T UNIX System V/386
This chip is detected and set by Mr.BIOS.

This chip can be detected by following sequence:

outb (inb (0x1F2) | 0x80, 0x1F2);
inb (0x1F5);
cli ();
inb (0x1F2);
inb (0x3F6);
inb (0x3F6);
inb (0x1F2);
inb (0x1F2);
sti ();
if (inb (0x1F2) & 0x80)
    printf ("Chip is not PDC20230-C");
else
    printf ("Chip is PDC20230-C");

Register 1F2
bit 7
bit 6 - 1 causes both devices maximum speed
bit 5
bit 4
bit 3 - always 1
bit 2
bit 1
bit 0

Register 1F3 - speed settings
bit 7 - unknown, set to 1 for speed setting 7 of device 0 or 1.
bit 6 - VL bus clock, 0 means > 33 Mhz, 1 means <= 33 MHz ?? allowed only for device 0 speed 7
bit 3,4,5 - speed setting of device 0 (master), 0 to 7
bit 0,1,2 - speed setting of device 1 (slave), 0 to 7
 

	bit 6 = 1	@ 33 MHz	bit 6 = 0	@ 50 MHz
Speed	Clocks	Cycle Time	Clocks	Cycle Time
0	21	630	31	620	PIO 0
1	20	600	28	560
2	17	510	26	520
3	16	480	25	500
4	13	390	20	400	PIO 1
5	12	360	19	380
6	9	270	15	300
7	8	240	12	240	PIO 2

After reset, lowest 3 bits of 1F3 registers contains speed setting set by jumpers (0, 2, 4, 6)

Writing new values ??? Is it really needed?

somedelay ();
outb (inb (0x1F2) | 0x01, 0x1F2);
somedelay ();
inb (0x1F5);

Register 1F5 - close programming mode
Reading from register 1F5 closes programming mode.

DOS driver for PDC20230-C uses VLB sync sequence for 32-bit I/O, but it seems it works without it.